As an insulated gate semiconductor device used for power devices, a trench gate semiconductor device having a trench gate structure has been proposed up until now. In the trench gate semiconductor device, a trade-off between high breakdown voltage and low on resistance is generally present.
The present applicants have proposed an insulated gate semiconductor device 900 shown in FIG. 11 as a trench gate semiconductor device which has solved such a problem (Japanese Patent Application No. 2003-349806). The insulated gate semiconductor device 900 is provided with N+-type source regions 31, an N+-type drain region 11, a P−-type body region 41, and an N−-type drift region 12. Also, gate trenches 21, which pass through the N+-type source region 31 and the P−-type body region 41, are formed by grooving parts of the top surface of the semiconductor substrate. In the lower part of the gate trench 21, a deposited insulating layer 23 comprised of an insulating material deposit is formed. On the deposited insulating layer 23, a gate electrode 22 is formed. The gate electrode 22 faces the N+-type source region 31 and the P−-type body region 41 via a gate insulating film 24 formed on the side of the gate trench 21. Further, P-type floating regions 51 are formed within the N−-type drift region 12. The lower end of the gate trench 21 is located within the P-type floating region 51.
Having the P-type floating regions 51 in the N−-type drift region 12, the insulated gate semiconductor device 900 has the following characteristics in comparison with insulated gate semiconductor devices having no floating region: a depletion layer is formed from the PN junction between the N−-type drift region 12 and the P−-type body region 41 by a voltage between the drain and the source (hereinafter referred to as “D and S”) during the switch-off of a gate voltage; electric field strength peaks near the PN junction; when the extremity of the depletion layer reaches the P-type floating regions 51, the regions 51 are placed into a punch-through state, so that its potential is fixed; when the applied voltage between D and S is high, depletion layers are also formed from the lower end of the P-type floating regions 51; the electric field strength also peaks near the lower end of the P-type floating regions 51 aside from the PN junction between the P−-type body region 41 and the N−-type drift region 12, that is, the peak of the electric field can be formed at two places, so that its maximum peak value is reduced, which allows a high breakdown voltage to be achieved; and the semiconductor device 900 with the high breakdown voltage is able to have a low on resistance through an increase in the impurity concentration of the N−-type drift region 12.
Additionally, as shown in FIG. 12, the gate trenches 21 of the insulated gate semiconductor device 900 are arranged in a striped shape in a cell area (within a broken-line box in FIG. 12). Further, in an terminal area (outside of the broken-line box X in FIG. 12), terminal trenches 62 are formed so as to encompass the cell area. Still further, P-type floating regions are also formed around the bottom of the terminal trenches. In this way, the breakdown voltage of the entire insulated gate semiconductor device 900 is increased. Examples of the semiconductor device in which the trenches are formed so as to encompass the cell area include, for example, a diode element disclosed in Patent Document 1.    [Patent Document 1] Japanese Published Unexamined Patent Application No. 2003-243671
However, the insulated gate semiconductor device 900 has the following problems: electrostatic focusing is relieved thickness-wise since the depletion layer formed from the PN junction between the N−-type drift region 12 and the P−-type body region 41 is connected with the depletion layers formed from the P-type floating regions 51; and electrostatic focusing is relieved sidewise since the depletion layers formed from the P-type floating regions 51 are connected with the depletion layer formed from the other P-type floating region.
The linkage of the depletion layer formed from the PN junction between the N−-type drift region 12 and the P−-type body region 41 and the depletion layers formed from the P-type floating regions 51 depends upon the thickness-wise structural design of the semiconductor substrate. Because of this, high breakdown voltage is reliably achieved by designing the structure in consideration of the thickness-wise spread of the depletion layers in advance. On the other hand, the linkages of the depletion layers formed from the P-type floating regions depend upon the sidewise structural design of the semiconductor substrate. Because of this, the high breakdown voltage is achieved by designing the structure in consideration of the sidewise spread of the depletion layers in advance. However, when there are variations in the distances between the P-type floating regions, the linkage of the depletion layers may not occur. As a result, the breakdown voltage may decrease at portions where the linkage of the depletion layers has not occurred.
For instance, the regions where the breakdown voltage of the insulated gate semiconductor device 900 decreases are as follows; the terminal trenches 62 within the terminal area are formed so as not to connect with the gate trenches 21 within the cell area as shown in FIG. 12, so that the gate trenches 21 have gaps; as shown in FIG. 13, portions where spacings between the side of the terminal trench 62 and the ends of the gate trenches 21 are long (L1<L2 in FIG. 13) are present near the gaps (within a solid-line box Y in FIG. 12); and this brings variations in spacings between the P-type floating regions around the bottom of the terminal trenches 62 and the P-type floating regions around the bottom of the gate trenches 21.
Also, near the corners of the terminal trench 62 (within the solid-line box Z in FIG. 12) among the gaps of the gate trenches 21, variations in the spacings between the ends of gate trenches 21 and the side of the terminal trench 62 clearly occur as shown in FIG. 14. This is because the respective gate trenches 21 formed in a striped shape are formed so as to have a uniform length and their ends are evened up in the direction of their length (see FIG. 12). Specifically, near the corners of the terminal trench 62, the closer the gate trenches 21 are formed toward the corners of the terminal trench 62, the narrower the spacings between the ends of the gate trenches 21 and the terminal trench 62 become (L1<L2<L3 in FIG. 14). Likewise, the closer the gate trenches 21 are formed toward the corners of the terminal trench 62, the narrower spacings between the P-type floating region 53 around the bottom of the terminal trench 62 and the P-type floating regions 51 around the bottom of the gate trenches 21 become.
Further, in order to solve these problems, it is also considered that the gate trenches 21 are linked with the terminal trench 62 as shown in FIG. 15. The gaps of the trenches can be eliminated by arranging each trench in such a way. However, when the trench junctions are formed by dry etching, the volume of etching gas entering the junctions is different from that entering the portions other than the junctions. Because of this, etching proceeds readily at the junctions, which makes the depths of the trenches uneven. FIG. 16 is a sectional view taken along the line C-C of the semiconductor device shown in FIG. 15. As shown in FIG. 16, the depth of the trench junctions is greater than that of the portions other than the junctions. As a result, the depth of the P-type floating region around the bottom of the linked trenches also becomes greater, which brings about a decrease in the breakdown voltage.
Still further, when the trenches are linked with each other, they also widen at their junctions. Because of this, the size of the P-type floating regions becomes larger than that based on their design value. As a result, the size of the N−-type drift region 12 is reduced, which makes on resistance high.
Furthermore, an insulating material is embedded in the gate trenches 21 of the insulated gate semiconductor device 900, after which the insulating material is etch-backed to form spaces. A conductor is embedded in the spaces formed by etch back to form the gate electrodes 22. At this time, when the trenches are wide, the insulating material cannot be embedded sufficiently, so that voids and so on may occur within the deposited insulating layers. When deposited insulating layers having voids are etch-backed, etching proceeds at the void portions rapidly to form wedge-shaped grooves in the deposited insulating layers. Then, a gate material gets into the wedge-shaped grooves, so that depletion layers spread into directions which are different from those based on their design. Because of this, unlike common trench gate semiconductor devices, it is preferable that the insulated gate semiconductor device 900 has no trench junction.
The present invention has been realized by solving the problems which the conventional insulating gate semiconductor device has. That is, an object of the invention is to provide an insulated gate semiconductor device which has floating regions around the bottom of trenches and which is capable of reliably exhibiting a high breakdown voltage.